This invention relates to a high performance printed wiring board structure having very high circuitry density per unit of area, and to a method of fabrication and utilization of such a printed wiring board structure.
With the recent strong trend toward reduced sizes in electronic components and the resulting high density requirements for electronic packaging such as printed wiring board structures, there have been increased demands to design a process that will generate high quality, high density printed wiring boards efficiently.
In the past decade the density per unit area of electronic devices, such as very large scale integrated circuits (VLSIs), has greatly increased. By some estimates this increase in density has been on the order of 10,000 times what it was in the earliest days of the technology. The space or area available outside of a VLSI in which to make the large number of necessary connections to and from it and to provide the necessary circuitry is becoming almost vanishingly small measured by previous standards. Contrary to the density increase of VLSIs, the density of the passive circuits on printed wiring boards has increased (i.e., the parts have decreased in size) by only a relatively small factor: less than about 4 to 1. This presents the difficult problem of providing circuitry on the printed wiring board to the VLSIs which is small enough to fit the spaces available and which is also sufficiently reliable and manufacturable to be economically useful.
Perhaps one of the most significant limitations on creating high density fine line circuitry on printed wiring boards is the generally known problem of anisotropic etching. It is known that etching metals, especially copper metal, is not an anisotropic process. That is, vertical etching is not feasible without some amount of unwanted horizontal etching. This creates a situation in which the features and circuitry so formed can be severely undercut, leading to different types of failures and reject material. The problem is exacerbated by having thick metal layers. However, this is precisely the situation that is created when standard vias or through holes are part of the manufacturing process.
It is well known that the plating within a through hole is thinner than the plating on the external surfaces; yet a minimum thickness in the through hole is required in order to provide an adequate and reliable electrical connection between circuitry on the opposing surfaces or at various levels within the printed wiring board. Therefore, the general practice is to plate excess material on the lateral faces in order to ensure sufficient plating of the through holes. The effect of this is that the greater than necessary thickness of the lateral surface plating then causes greater amounts of undercutting during the circuitization/etching process. To compensate for this effect, the circuitry lines are designed wider and farther apart than otherwise required or desired. To resolve this problem, thinning down the lateral surface by etching, prior to circuitization, has been attempted. If chemically performed, this process also undesirably etches within the plated through hole. Mechanical etching of the lateral surface plating is possible, but general practice for a process of this type is very slow.
Hayakawa et al. in U.S. Pat. No. 4,383,363, teach the use of conductive materials for filling through holes but no mention is made of non-conductive materials for this application. Hayakawa et al. do not disclose the significance of a thin metallic layer for creating high density circuitry. The purpose of the conductive filling in their invention is solely to electrically connect the two major faces of the substrate, not to protect the metallized layer in the through hole, as in the present invention.
Kawakami et al. in U.S. Pat. No. 5,220,135, disclose a conductive filling within the through hole of an insulative substrate. As in U.S. Pat. No. 4,383,363, supra, no mention is made of protecting the metallized layer within the plated through hole.
Bhatt et al. in U.S. Pat. Nos. 5,557,844 and 5,487,218, disclose a process and a material for forming filled through holes and blind holes. The filler material is an organic polymeric material optionally with a particulate filler. The filler composition is compounded to have a coefficient of thermal expansion matching the coefficient of thermal expansion of the dielectric substrate. The fill material may be either conductive or non-conductive. These patents teach first laminating a copper foil to a dielectric substrate followed by thinning the foil to an acceptable thickness, then drilling through holes and subsequently electroless plating into the through holes to create a conductive layer therein. The filling in the ""844 patent occurs after the etching process of the lateral metallized layers, unlike the present invention which requires that the filler be present during the etching process. Furthermore, the specific benefit of the present invention is that both the lateral metallic layers and the through hole metallized layer are applied simultaneously, unlike the ""844 disclosure which specifies that these steps occur sequentially.
Having discussed the general problem and the current attempts at the problem, it is understood that various improvements would be beneficial.
Therefore, it is an object of the current invention to provide a high density (low pitch) fine line circuitry printed wiring board structure.
It is another object of the invention to provide thin surface layer circuitry.
It is another object of the invention to protect the plating within plated through holes.
It is yet another object of the invention to provide a high density (low pitch) fine line circuitry printed wiring board having multiple layers of circuitry interconnected through plated through holes or blind holes.
Yet another object if this invention is to provide a method of making a circuitized substrate capable of being used as a chip carrier assembly. The method can be performed in a facile and relatively inexpensive manner in comparison to existing carrier manufacturing processes.
It is still another object of the invention to provide circuitry and features that have a smaller height than via plating thickness in order to maximize interlayer reliability and to minimize pitch distance for surface features.
It is a more particular object of the invention to provide such a process which is readily adaptable to existing manufacturing equipment without extensive modification thereof.
In accordance with one aspect of this invention, there is defined a method of making a circuitized substrate, the method comprising the steps of providing an electrically insulative base member (dielectric substrate) having first and second lateral surfaces, forming at least one via hole, applying a first electrically conductive layer onto the first and second surfaces of the base member, including at least one sidewall of the via, filling the via with a non-conductive material, planarizing at least one of the first and second surfaces, thinning the first conductive layer on the first and second surfaces, and performing a second planarization of the thinned first electrically conductive layer. The method still further includes applying a photoimaging material onto the thinned first conductive layer then exposing and developing selected portions of the photoimaging material to define a pattern within the photoimaging material on the thinned first conductive layer. The method further includes circuitizing the thinned first conductive layer and then removing the photoimaging material from the thinned first conductive layer. The fill material contained in the plated vias is not removed during this or later processes.
The inventive method involves protecting the metallized layer within a via such as a through hole or blind hole from being chemically etched during later manufacturing steps. In order to protect this metallized layer, a filling material is injected into the hollow region of the plated through hole to essentially prevent chemical etchants from contacting and attacking its surface. Ideally, the material should substantially fill the plated through hole. If additional filling is inadvertently applied, a planarization process can be performed to achieve coplanarity between the outer surface of the filling material and the outer surface of the lateral metallized layer.
When the filling material is coplanar it can be used as an area to additionally support the application of liquid or dry film photoresists. These photoresists are necessary to personalize or circuitize the lateral metallized or conductive layers. The photoresist should make intimate contact with the lateral surface. Having a filled through hole assists in achieving that goal. The filled through hole allows the use of liquid photoresists that ordinarily would not be capable of being used with standard open ended plated through holes unless other steps are performed.
One benefit of the present invention is the ability to produce higher density circuitry than is currently available from existing designs. This invention can produce circuitry having a cross-section width of 0.7-2.0 mil and spacing between the circuitry of 0.5-2.0 mil. No other photolithographic processes are known to the inventors that can generate these same dimensions.
Other benefits and further scope of applicability of the present invention will become apparent from the detailed description given hereinbelow. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope and spirit of the invention will become apparent to those skilled in the art from this detailed description.